ARM7 TDMI Manual Pt3

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1 11 5 THUMB Instruction Set This chapter describes the THUMB instruction set. Format Summary Opcode Summary Format 1: move shifted register Format 2: add/subtract Format 3: move/compare/add/subtract immediate Format 4: ALU operations Format 5: Hi register operations/branch exchange Format 6: PC-relative load Format 7: load/store with register offset Format 8: load/store sign-extended byte/halfword Format 9: load/store with immediate offset Format 10: load/store halfword Format 11: SP-relativ
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  ARM7TDMI Data Sheet ARM DDI 0029E 5-1 11 1      O  p  e  n   A  c  c  e  s  s THUMB Instruction Set This chapter describes the THUMB instruction set.Format Summary5-2Opcode Summary5-35.1Format 1: move shifted register5-55.2Format 2: add/subtract5-75.3Format 3: move/compare/add/subtract immediate5-95.4Format 4: ALU operations5-115.5Format 5: Hi register operations/branch exchange5-135.6Format 6: PC-relative load5-165.7Format 7: load/store with register offset5-185.8Format 8: load/store sign-extended byte/halfword5-205.9Format 9: load/store with immediate offset5-225.10Format 10: load/store halfword5-245.11Format 11: SP-relative load/store5-265.12Format 12: load address5-285.13Format 13: add offset to Stack Pointer5-305.14Format 14: push/pop registers5-325.15Format 15: multiple load/store5-345.16Format 16: conditional branch5-365.17Format 17: software interrupt5-385.18Format 18: unconditional branch5-395.19Format 19: long branch with link5-405.20Instruction Set Examples5-42 5  THUMB Instruction Set ARM7TDMI Data Sheet ARM DDI 0029E 5-2    O  p  e  n   A  c  c  e  s  s Format Summary The THUMB instruction set formats are shown in the following figure. Figure 5-1: THUMB instruction set formats  1514131211109876543210 1 000OpOffset5RsRd Move shifted register  2  00011IOpRn/offset3RsRd Add/subtract  3  001OpRdOffset8 Move/compare/add /subtract immediate  4  010000OpRsRd ALU operations  5  010001OpH1H2Rs/HsRd/Hd Hi register operations /branch exchange  6  01001RdWord8 PC-relative load  7  0101LB0RoRbRd Load/store with register offset  8  0101HS1RoRbRd Load/store sign-extended byte/halfword  9  011BLOffset5RbRd Load/store with immediate offset  10  1000LOffset5RbRd Load/store halfword  11 1001LRdWord8 SP-relative load/store  12  1010SPRdWord8 Load address  13  10110000SSWord7 Add offset to stack pointer  14  1011L10RRlist Push/pop registers  15  1100LRbRlist Multiple load/store  16  1101CondSoffset8 Conditional branch  17  11011111Value8 Software Interrupt  18  11100Offset11 Unconditional branch  19  1111HOffset Long branch with link  1514131211109876543210  THUMB Instruction Set ARM7TDMI Data Sheet ARM DDI 0029E 5-3    O  p  e  n   A  c  c  e  s  s Opcode Summary The following table summarizes the THUMB instruction set. For furtherinformation about a particular instruction please refer to the sections listed in theright-most column. MnemonicInstructionLo registeroperandHi registeroperandConditioncodes setSee Section: ADCAdd with Carry  5.4ADDAdd  5.1.3, 5.5, 5.12, 5.13ANDAND  5.4ASRArithmetic Shift Right  5.1, 5.4BUnconditional branch  5.16B xx  Conditional branch  5.17BICBit Clear  5.4BLBranch and Link5.19BXBranch and Exchange  5.5CMNCompare Negative  5.4CMPCompare  5.3, 5.4, 5.5EOREOR  5.4LDMIALoad multiple  5.15LDRLoad word  5.7, 5.6, 5.9, 5.11LDRBLoad byte  5.7, 5.9LDRHLoad halfword  5.8, 5.10LSLLogical Shift Left  5.1, 5.4LDSBLoad sign-extendedbyte  5.8LDSHLoad sign-extendedhalfword  5.8LSRLogical Shift Right  5.1, 5.4MOVMove register  5.3, 5.5MULMultiply  5.4MVNMove Negative register  5.4 Table 5-1: THUMB instruction set opcodes   THUMB Instruction Set ARM7TDMI Data Sheet ARM DDI 0029E 5-4    O  p  e  n   A  c  c  e  s  s  The condition codes are unaffected by the format 5, 12 and 13versions of this instruction.  The condition codes are unaffected by the format 5 version of thisinstruction. NEGNegate  5.4ORROR  5.4POPPop registers  5.14PUSHPush registers  5.14RORRotate Right  5.4SBCSubtract with Carry  5.4STMIAStore Multiple  5.15STRStore word  5.7, 5.9, 5.11STRBStore byte  5.7STRHStore halfword  5.8, 5.10SWISoftware Interrupt5.17SUBSubtract  5.1.3, 5.3TSTTest bits  5.4 MnemonicInstructionLo registeroperandHi registeroperandConditioncodes setSee Section: Table 5-1: THUMB instruction set opcodes (Continued) 
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